1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating thereof. Particularly, this invention relates to a semiconductor device having a plurality of metal layers with wiring patterns positioned for avoiding cracks at insulating spaces.
2. Description of the Related Art
As part of the recent trend toward larger scale integration of semiconductor devices, the devices have evolved from having a conventional single or dual metal layer structure to having a multilevel metal layer structure. Chemical vapor deposition (CVD) is widely used to form an insulating layer between every pair of metal layers and between portions of a wiring pattern formed in the metal layer.
The advantages of CVD include a high deposition rate and easy control over deposition thickness. However, a CVD film has a relatively low strength. That is to say, a CVD film deposited on a metal layer may crack, depending on the thermal state and pattern of metal in the metal layers. Cracks generally occur due to unbalanced stress from differences in thermal expansion between the metal in a metal layer and the CVD film in insulating layers between the metal layers and in insulating spaces within each metal layer. In a multilevel metal layer device, especially in a metal layer having a wiring pattern with widths of 30 micrometers (.mu.m) or more, the probability of cracking is higher than in devices with fewer metal layers and narrower wiring patterns. This greater probability of cracking arises because vertical expansion is greater over several stacked metal wiring patterns than over fewer stacked metal wiring patterns and horizontal expansion is greater for wide patterns than for narrow patterns. In these circumstances the stresses due to difference in thermal expansion between the metal and the insulating CVD material is increased, and as more stresses accumulate the more cracks that occur.
FIGS. 1A and 1B show a crack occurring in a semiconductor device having multilevel metal layers. As shown in FIG. 1A, horizontally oriented metal layers 111, 112 and 113 are separated vertically by interposed insulating layers 116, 117, and 118. Within a given metal layer, e.g., 112, one or more metal wiring patterns, e.g., 115 and 115', are separated by one or more insulating spaces 212 according to a wiring pattern design. The insulating spaces 212, 213 have width d1. FIG. 1A shows a vertical crack 110 which occurs through the spaces 213, 212 between metal wiring patterns 114 and 114', and 115 and 115', respectively. The crack 110 crosses the interposed insulating layers 118, 117 and 116 vertically separating the metal layers 113, 112 and 111.
FIG. 1B shows the horizontal aspect of a crack 120. The horizontal crack 120 occurs in an insulating space 203 between parallel metal wiring patterns of one metal layer 103 where the width of the wiring pattern is greater than the width d1' of the insulating space 203. Specifically, FIG. 1B shows that, in metal layer 103 where wide metal wiring patterns are juxtaposed to narrow insulating spaces 203, a crack 120 longitudinally occurs at a space between the metal wiring patterns. The crack has both a horizontal aspect occurring in an insulating space 203 between the parallel metal wiring patterns of one metal layer 103 and a vertical aspect occurring through the insulating spaces 203, 202 and 201 of each metal layer 103, 102 and 101 and through the interposed insulating layers.
Referring again to FIG. 1A, it is noted that the vertical aspect of the crack 110 occurs because the vertical column of pure CVD material in the spaces 212 and 213 expands much differently than other columns of alternating metal and CVD layers. Therefore vertical tensile stresses at the vertical column through the edges of the wiring patterns 115 and 114 in each metal layer are accumulated until those stresses exceed the strength of the CVD film, and the CVD film cracks. Since metal is more malleable than the CVD material, the metal may deform but it does not crack at such stresses.
A typical semiconductor device manufacturing process includes many steps carried out at a temperature of 400.degree. C. or more, followed by other steps closer to room temperature. The metal layers are thermally expanded during the high temperature processes, and contracted when exposed to a room temperature. Thermal expansion is proportional to size and is typically greater for metals than for CVD materials. Accordingly, in the structure shown in FIG. 1A, in which the insulating spaces 213 and 212 are stacked one above another, the thick column of CVD material expands/contracts only a little, while the columns with metal wiring patterns in the metal layers expands/contracts more. This introduces an accumulated stress that can exceed the strength of the CVD material for certain temperature changes. Especially when the insulating spaces 213, 212 between wiring patterns 114, 114', 115, 115' have a size d1 less than 4 .mu.m, the horizontal thermal expansion difference between the metal wiring pattern and the CVD film adds to the total stress and increases the probability of cracking.
The horizontal crack 120 in FIG. 1B occurs when the horizontal thermal expansion of the metal wiring pattern is far greater than that of a CVD film, which is typically an oxide. When the CVD material in the insulating spaces 203, 202, 201 cannot withstand the expansion/contraction cycle of the metal wiring patterns any longer, the CVD film finally cracks at a narrow insulating space 203 of size d.sub.1. Since a CVD film is deposited on the expanded metal at high temperature above 400.degree. C. and is later exposed to room temperature, the stresses are applied at the interface between the metal wiring pattern and the CVD film. As in the vertical crack, the metal in the metal layer 101, 102, 103 is a soft material, i.e., it is malleable, at room temperatures so it does not crack easily; while the CVD film is a hard material so that it cracks first. This phenomenon becomes greater if the metal wiring pattern includes some with lengths and widths greater than the device size. (The width of the metal wiring pattern is typically below 30 .mu.m.) The larger wiring patterns expand/contract more than the smaller wiring patterns, adding to the stresses on the CVD film at some locations of the wiring pattern.
If a crack 110, 120 occurs, electrons can leak out along the crack 110, 120 opening and subsequent metal layers, e.g., 103, may fill the crack and connect to other layers, e.g., 102, thus bridging the metal layers and causing an electrical short, so that the insulation efficacy of the device's insulating layers is deteriorated and may cause the device to be defective. A very severe defect is especially likely because, in a multilevel metal layer device, a tungsten layer typically is deposited on the full area of the device to interconnect contacts, so a crack is likely to lead to a short.
Accordingly, a semiconductor device design is needed that prevents insulating spaces from cracking, especially for a multilevel metal layer structure for which the probability of cracking is greater than for a single or dual metal layer structure.